A silicon-on-insulator (SOI) integrated circuit typically includes a plurality of spaced, isolated islands of single-crystalline silicon on the surface of an insulator, e.g. a sapphire, substrate. Each island generally includes a MOSFET which has source and drain regions spaced by a channel region, a channel oxide layer over at least the channel region and a conductive gate on the oxide layer and over the channel region. The various MOSFETs are electrically connected to form a desired circuit, such as a complementary MOS (CMOS) integrated circuit. The MOSFETs are typically electrically connected, at least in part, by conductive interconnects of doped polycrystalline silicon which extend over the surface of the substrate between the various silicon islands.
The insulating material of the substrate for the fabrication of MOSFETs may be monocrystalline, e.g. sapphire, beryllia or spinel, or may be amorphous, e.g. quartz (glass). When the substrate insulating material is monocrystalline, the devices are generally referred to as SOS (silicon-on-sapphire) devices. Devices having an amorphous insulating substrate are generally referred to as poly-on-glass. These designations will be utilized herein.
In the fabrication of poly-on-glass or SOS devices, following the formation of one or more silicon islands on the substrate surface, a gate oxide is formed so as to selectively overlie a portion or portions of the silicon island(s). A conductive gate electrode, typically of doped polycrystalline silicon, is then formed over the gate oxide so as to be capacitively coupled to a portion of the underlying silicon island. A high quality device requires a high quality silicon dioxide dielectric. Such a dielectric is provided in copending U.S. patent application Ser. No. 793,312, METHOD OF FORMING AN IMPROVED GATE DIELECTRIC FOR A MOSFET ON AN INSULATING SUBSTRATE, A.C. Ipri, filed Oct. 31, 1985. While this method produces a superior gate dielectric, it is limited in that the oxide on the sidewalls of the silicon islands is of approximately the same thickness as that on the top of the islands. Ideally, the gate dielectric layer on the top of the islands should be relatively thin and that on the sides substantially thicker to protect the device and prevent breakdown. A method of forming such a structure is provided in accordance with this invention.